question 1: cache associativity and miss rate (10 points for each part) (a) if the instruction cache is a direct mapped cache of 4 blocks with each block of size 4 words. what is the miss rate for the above mips code? given that the pc corresponding to the start of the mips code is 0x48008, i.e., the program is stored in the memory starting from address 0x48008. (b) for a 2-way set associative data cache of 8 blocks each of 2 words, what is the miss rate following the lru scheme for replacement? (c) for a fully associative data cache of 8 blocks each of 2 words, what is the miss rate following the lru scheme for replacement?