Two important parameters control the performance of a processor: cycle time and cycles per instruction. There is an enduring trade-off between these two parameters in the design process of microprocessors. While some designers prefer to increase the processor frequency at the expense of large CPI, other designers follow a different school of thought in which reduce the CPI comes at the expense of lower processor frequency. Consider the following machines, and compare their performance assuming the frequency of instruction usage: Load, Store, R-type and Branch/Jump are 20%, 15%, 55%, and 10% respectively. 2 M1: The multicycle datapath with 4GHz clock. 2 M2: A machine is similar to the multicycle datapath, except that register updates are done in the clock cycle as a memory read or ALU operation. Thus Execution and WriteBack cycles are combined for R-type instructions, Memory and WriteBack cycles are combined for Load instruction. This machine has a 3.2GHz clock, since the register update increases the length of the critical path. 2 M3: A machine is similar to M2 except that effective address calculations are done in the same clock cycle as a memory access. Thus Execution and WriteBack cycles are combined for R-type instructions, Execution, Memory and Write Back cycles are combined for Load instruction, while Execution and Memory cycles are combined for Store instruction. This machine has a 2.8GHz clock because of the long cycle created by combining address calculation and memory access. 2 Find out which of the machines is fastest. Are there instruction mixes that would make another machine faster, and if so, what are they?