Determine which bits in a 32-bit address are used for selecting the byte (B), selecting the word (W), indexing the cache (I), and the cache tag (T), for each of the following caches: A. Direct-mapped, cache capacity = 64 cache line, cache line size = 8-byte, word size = 4-byte B. Fully-associative, cache capacity= 256 cache line, cache line size = 16-byte, word size = 4-byte C. 4-way set-associative, cache capacity = 4096 cache line, cache line size = 64-byte, word size = 4-byte Note: cache capacity represents the maximum number of cache blocks (or cache lines) that can fit in the cache 10