Consider the delays from the Table below. Now, suppose that the ALU were 20% faster. Would the cycle time of the pipelined RISCV processor change? What if the ALU were 20% slower? Explain your answers .
Component Delay Delay
Register Delay (Clk to Q) 40
Register Setup 50
Multiplexer 30
AND-OR gate 20
ALU 120
Decoder (Control Unit) 25
Sign Extend Unit 35
Memory Read 200
Register File Read 100
Register File Setup 60