Consider the following SystemVerilog module. State what the problem is and what
the likely problem would be with the hardware.
module ex8(input logic [2:0] a,
output logic y, z);
always_comb
case (a)
3’b000: {y, z} = 2’b11;
3’b001: {y, z} = 2’b01;
3’b010: {y, z} = 2’b10;
3’b011: {y, z} = 2’b00;
3’b100: {y, z} = 2’b10;
3’b101: {y, z} = 2’b10;
endcase
endmodule