Design a timing circuit that provides an output signal that stays on for twelve clock cycles. A start signal should set the output to 1 for twelve clock cycles. After the 12 cycles the output should go back to 0. For simplicity, assume the start input will be synced with the clock. Draw a state diagram with two states, init and wait. The circuit operates based on the values of two inputs, the start signal (S) and the count complete (C) signals. Assume that the C input is derived from the count of a 4-bit counter with parallel load. Show how to configure the counter to produce the C input properly.