Decade counter (mod-10 counter) A decade counter counts from 0 to 9 and warps around. Its inputs are: - clk10: clock signal - clear10: clear the counter to 00 - en10: enable the counting when en10 is 1 and pause otherwise. Its outputs are: - q3,q2,q1,q0:4-bit counting value ( q3 is MSB) - p10: an output pulse asserted when the counting value is 1001 and en10 is 1 .
(a) Design the decade counter using one 74163 and a minimal number of basic gates.
(b) Create a project in Altera Quartus II software and enter the schematic.
(c) Create a testing waveform with a clock period of 200 ns. The simulation should run at leas 30 clock cycles and verify the operation of the en10 input and the p10 output.