Design a 3 bit counter that counts in this sequence: 000,011,110,100,111 and repeats. An output Z should be a 1 only when state 111 occurs.
If the unused states should occur, the counter next state should be 000. Use three flip-flops named C, B, A. System clock is CLK.
Create the logic equations for the three flip-flop D inputs and the output Z. Schematic is not required. The design should use minimal logic.