Step 2: Write the code for a 16-bit adder adder dataa[15:0] sum[15:00 - datab[15:0] 1. Create a VHDL file using the Quartus Prime text editor: a. From the Quartus Prime File menu select New or click on the button. b. The New File dialog box will appear; select VHDL File. c. Click OK. 2. Write the source code for a 16-bit adder using the "+' operator. Use the following information as a guide: a. Use the names in the Adder Symbol/diagram above to name your block and its ports (all lower-case). For example dataa[15:0] signal name in VHDL would be dataa : in unsiged (15 downto 0); 10 VHDL Exercises b. All inputs and outputs should be declared as type UNSIGNED vs STD LOGIC VECTOR. c. Do not worry about rollover with this adder. This adder is already wide enough to account for all the values it will be adding together.