Estimate i) the dynamic power consumption and ii) the EDP (evergy delay product) of whole chip if it has an area of 100 mmand runs at 500 MHz for 10 nono seconds at VDD = 0.8 V with 20 percent toggle rate. You are using a standard cell process with an average switching capacitance of 600 pF/mm². 2) You are considering lowering VDD to 0.6 V to try to save power in a static CMOS gate. You will also scale Vt proportionally to maintain performance. i) Will dynamic power consumption go up or down? ii) Will static power consumption go up or down? Please explain the reasoning of your answer.