How to write the VHDL code for the following project?

Design and simulation of a final state machine (FSM) that describes the functionality of a Traffic Light system using two approaches:

1. Traditional approach employing small scale logic components

2. Modern approach using behavioural modelling with VHDL.

A Traffic Light system at a road intersection has a finite number of states that the light could be in. The sequence of different states. The lights have different time periods. For example, the green light remains longer than the red in both directions. The traffic light in the intersection works as follows:

For a short period of time the lights are red in both directions (vertical and horizontal) for 5 seconds.

The lights do not change directly from red to green. They first change to red and yellow simultaneously for 6 seconds.

After the red/yellow lights, the green light lasts for 80 seconds.

The lights then changed into yellow for 6 seconds.