The block diagram of FIGURE 1 shows a 3-stage asynchronous counter that is used to count a series of randomly occurring input pulses.
The q outputs of the counter are used to drive a logic circuit that gives the output in TABLE 1.
Design the logic circuit to realise the desired ABCD outputs.
____________
in │ Counter │
→ │ │
___▯___▯__▯_▯→ t │ Q1 Q2 Q3 │
│ │ │
│ │ │ ________
│ │ │ ----→│ │--- A
│ │-----------→│ Logic │--- B
│------------------→│ │--- C
│_______│--- D

Input Pulse D C B A
0 0 0 0 0
1 0 0 0 1
2 0 0 1 1
3 0 1 1 1
4 1 1 1 1
5 1 1 1 0
6 1 1 0 0
7 1 0 0 0
8 0 0 0 0
9 0 0 0 1
etc
TABLE 1