The circuit below describes a 4-to-1 multiplexer with data inputs I3, I2, I1 and I0 and selects S1 and S0. Draw the multiplexer circuit described by the VHDL below. In0Sel <= NOT S1 AND NOT S0 AND I0; In1Sel <= NOT S1 AND S0 AND I1; In2Sel <= S1 AND NOT S0 AND I2; In3Sel <= S1 AND S0 AND I3; Y <= In0Sel OR In1Sel OR In2Sel OR In3Sel;