When the value of the valid/invalid bit for a page reference results in a page fault, that bit is not implicated.
The related page is a legal (or valid) page if it is in the process' logical address space and has this bit set to valid/invalid bit. The page is not within the logical address space of the process when the bit is set to invalid. This is, in my opinion, somewhat incomplete or misleading.
A cache system can use valid bits to determine whether it needs to fetch the right data from the main memory (RAM). "An instruction cache just needs one valid/invalid bit per cache row entry. A cache block's valid bit shows whether or not it has been loaded with valid data.
A set valid/invalid bit indicates that there is mail in the box.
Learn more about valid/invalid bit here
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