Respuesta :
A given processor with a 4-wide issue and 25 pipeline stages has a maximum of 100 instructions in flight.
The throughput of a CPU is increased through pipelining. The clock speed of the chip can be increased by adding pipeline stages because each step can operate more quickly. The number of instructions that may be performed at once grows with the number of pipeline stages.
However, the additional pipeline registers will result in an increase in the latency of individual instructions. Additionally, the cost of space and electricity for the pipeline registers has increased. The fact that expanding pipeline stages only works if you have instructions to feed the pipeline is a major problem. Additionally, branch mispredictions can be particularly expensive because a longer pipeline can result in more computation being "wasted" on a branch misprediction. As a result of the error, the obtained throughput is likewise less than the maximum achievable.
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