This problem has 4 answers (3 modules + one explanation). In a
module named "extend", do the following: create the 8-bit output named signext, which is
the sign-extended version of a[2:0] (the module’s input). Also create the 8-bit output
named zeroext, which is the zero-extended version of a[2:0].
Write three versions of a SystemVerilog module to implement these operations using:
(i) assign statement (must be outside of an always block)
(ii) if/else statements (must be inside an always block)
(iii) case statements (must be inside an always block)
After writing the modules, comment about which version you would pick to implement
this function. Explain.
PLEASE DO part (ii) and part (iii)