One main drawback of a basic S (set) - R (reset) latch is that SR=11 is usually undesired. So we make them forbidden (not supposed to be used for the design). 1234567​ module basicSRLatch(input logic S, input logic R, output logic Q, output logic QN); assign Q=∼(R∣QN); assign QN=∼(S∣Q); endmodule ​ A new set-dominant SR latch will work the same way as the basic SR latch without its drawback above. In case of SR=11, a set-dominant SR latch will take the action of Set. Choose the correct systemVerilog statement for the setdominant SR latch module below.