We begin with a computer implemented in single-cycle implementation. When the stages are split by functionality, the stages do not require exactly the same amount of time. The original machine had a clock cycle time of 7ns. After the stages were split, the measured times were IF, Ins; ID, 1.5 ns; EX, Ins; MEM, 2ns; and WB, 1.5ns. The pipeline register delay is 0. Ins.
a) What is the clock cycle time of the 5-stage pipelined machine?
b) If there is a stall after every 4 instructions, what is the CPI of the new machine?
c) What is the speedup of the pipelined machine over the single-cycle machine?
a) (a) 2 ns (b) Steady state CPI = 1.25 ((No of instructions + no of stalls) no of instructions) (c) 2.67